In silicon integrated circuit technology, a large number of isolated devices are fabricated on the same semiconductor substrate. Subsequently these devices are interconnected along specific paths to create the desired circuit configuration. In the continuing trend toward higher densities, devices are placed closer together with smaller spaces between them. Device isolation, which is critical to proper circuit operation, has become progressively more challenging.
Over the last few decades a variety of isolation technologies have been developed to address the requirements of various integrated circuit types. In general, the various isolation technologies are different with respect to characteristics such as minimum isolation spacing, surface planarity, process complexity and defect density generated during isolation processing. Moreover, it is common to make trade-offs among these characteristics when developing an isolation process for a particular integrated circuit application.
In MOS (metal-oxide-semiconductor) technology, LOCOS isolation (LOCal Oxidation of Silicon) has been the most widely used isolation technology. LOCOS isolation involves thermal oxidation of a silicon substrate through a mask. The resultant field oxide is generally grown thick enough to avoid cross-talk between adjacent devices, but not so thick as to cause step coverage problems. The great popularity of LOCOS isolation technology can be attributed also to its inherent simplicity in MOS process integration, its cost effectiveness and its adaptability.
In spite of its success, several limitations of LOCOS technology have driven the development of alternative isolation structures. A well-known limitation in LOCOS isolation is oxide undergrowth at the edge of the hard mask (typically made of silicon nitride) that protects the active regions of the substrate during oxidation. This so-called “bird's beak” poses a limitation to device density since it widens the isolation region, thereby reducing resolution, while causing stress within the substrate. Another problem associated with the LOCOS process is its non-planarity. For submicron devices, non-planarity becomes an important issue, often posing problems for photolithography and subsequent layer conformality.
Trench isolation technology has been developed, in part, to overcome the aforementioned limitations of LOCOS isolation for submicron devices. Refilled trench structures comprise a recess formed in the silicon substrate, which is filled with a dielectric material. Such structures are fabricated by first forming submicron-sized trenches in the silicon substrate, usually by a dry anisotropic etching process through openings in a photoresist overlayer. Typically the resulting trenches display a steep sidewall profile. The trenches are refilled with a dielectric material, such as silicon dioxide (SiO2), usually deposited by a chemical vapor deposition (CVD) or spin-on glass (SOG) process. Then the surface is smoothed by an etchback or polishing process so that the trench is completely filled with the dielectric material, and its top surface is level with the silicon substrate. After a successful etchback, the top surface has good planarity and is at the same level as the surrounding substrate. The resulting structure serves to electrically isolate adjacent devices.
Refilled trench isolation can take a variety of forms depending upon the specific application. It is generally categorized in terms of the trench dimensions: shallow trenches (<1 μm deep), moderate depth trenches (1-3 μm deep), and deep, narrow trenches (>3 μm deep, <2 μm wide). Shallow Trench Isolation (STI), for example, is used primarily for isolating devices of the same type and is often considered an alternative to LOCOS isolation. Furthermore, shallow trench isolation has the advantages of eliminating the bird's beak of LOCOS and providing a high degree of surface planarity.
The basic trench isolation process is, however, subject to drawbacks, including void formation in the trench during dielectric refill. Voids result when the refilling dielectric material forms a constriction near the top of the trench before it is completely filled, as shown in FIG. 1A. Such voids compromise device isolation as well as the overall structural integrity of the integrated circuit. Unfortunately, preventing void formation during trench refill often places minimum size constraints on the trenches themselves, which can limit device packing density or the effectiveness of the device isolation. A key parameter in measuring the effectiveness of device isolation is the field threshold voltage, that is, the voltage necessary to create a parasitic current linking adjacent isolated devices. The field threshold voltage is influenced by a number of physical and material properties, such as trench width, dielectric constant of the trench filling material, substrate doping, field implant dose and substrate bias.
Generally, void formation has been mitigated by decreasing trench depth and/or tapering trench sidewalls so that the openings are wider at the top than at the bottom, as shown in FIG. 1B. A principal trade off in decreasing the trench depth is reducing the effectiveness of the device isolation, while the larger top openings of trenches with tapering sidewalls use up additional and valuable integrated circuit real estate.
Accordingly, it is desirable to develop a trench isolation process that overcomes the problem of void formation while providing effective device isolation.